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HEF4017B
5-stage Johnson decade counter
Rev. 04 -- 9 December 2008 Product data sheet
1. General description
The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0, CP1). Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over both the industrial (-40 C to +85 C) and automotive (-40 C to +125 C) temperature ranges.
2. Features
I I I I I I I I Automatic counter correction Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range -40 C to +125 C Complies with JEDEC standard JESD 13-B ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V
3. Applications
I Industrial and automotive
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
4. Ordering information
Table 1. Ordering information All types operate from -40 C to +125 C Type number HEF4017BP HEF4017BT Package Name DIP16 SO16 Description plastic dual in-line package; 16-leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1
5. Functional diagram
13 14 15
CP1 CP0 MR 5-STAGE JOHNSON COUNTER
DECODING AND OUTPUT CIRCUITRY Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 3 2 4 7 10 1 5 6 9 11
Q5-9
12
001aah242
Fig 1.
Functional diagram
CP1
CP0
Q FF 1 CP Q RD
D
Q FF 2 CP Q RD
D
Q FF 3 CP Q RD
D
D
Q FF 4 CP Q RD
D
Q FF 5 CP Q RD
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q5-9
001aah243
Fig 2.
Logic diagram
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
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NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
14 13 14 CP1 CP0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 15 MR Q7 Q8 Q9 Q5-9
001aah239
CTRDIV10/DEC & CT = 0 0 1 2 3 4 5 6 7 8 9 CT5
001aah240
3 2 4 7 10 1 5 6 9 11 12
3 2 4 7 10 1 5 6 9 11 12
13 15
Fig 3.
Logic symbol
Fig 4.
IEE logic symbol
6. Pinning information
6.1 Pinning
HEF4017B
Q5 Q1 Q0 Q2 Q6 Q7 Q3 VSS 1 2 3 4 5 6 7 8
001aae574
16 VDD 15 MR 14 CP0 13 CP1 12 Q5-9 11 Q9 10 Q4 9 Q8
Fig 5.
Pin configuration
6.2 Pin description
Table 2. Symbol Q0 to Q9 VSS Q5-9 CP1 Pin description Pin 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 8 12 13 Description decoded output ground supply voltage carry output (active LOW) clock input (HIGH-to-LOW edge-triggered)
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
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NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 2. Symbol CP0 MR VDD
Pin description ...continued Pin 14 15 16 Description clock input (LOW-to-HIGH edge-triggered) master reset input supply voltage
7. Functional description
Table 3. MR H L L L L L L
[1]
Function table [1] CP0 X H L X H CP1 X L X H L Operation Q0 = Q5-9 = H; Q1 to Q9 = L counter advances counter advances no change no change no change no change
H = HIGH voltage level; L = LOW voltage level; X = don't care; = positive-going transition; = negative-going transition.
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
4 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
CP0 INPUT
CP1 INPUT
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q5-9 OUTPUT
001aah244
Fig 6.
Timing diagram
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O Parameter supply voltage input clamping current input voltage output clamping current input/output current VO < 0.5 V or VO > VDD + 0.5 V VI < 0.5 V or VI > VDD + 0.5 V Conditions Min -0.5 -0.5 Max +18 10 VDD + 0.5 10 10 Unit V mA V mA mA
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
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NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol IDD Tstg Tamb Ptot Parameter supply current storage temperature ambient temperature total power dissipation Tamb = -40 C to +125 C DIP16 package SO16 package P
[1] [2]
[1] [2]
Conditions
Min -65 -40 -
Max 50 +150 +125 750 500 100
Unit mA C C mW mW mW
power dissipation
per output
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 5. Symbol VDD VI Tamb t/V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 -40 Typ Max 15 VDD +125 3.75 0.5 0.08 Unit V V C ns/V ns/V ns/V
10. Static characteristics
Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 A VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 A 5V 10 V 15 V VOH HIGH-level |IO| < 1 A; output voltage VI = VSS or VDD LOW-level |IO| < 1 A; output voltage VI = VSS or VDD 5V 10 V 15 V VOL 5V 10 V 15 V Tamb = -40 C Min 3.5 7.0 11.0 4.95 9.95 14.95 Max 1.5 3.0 4.0 0.05 0.05 0.05 Tamb = 25 C Min 3.5 7.0 11.0 4.95 9.95 14.95 Max 1.5 3.0 4.0 0.05 0.05 0.05 Tamb = 85 C Min 3.5 7.0 11.0 4.95 9.95 14.95 Max 1.5 3.0 4.0 0.05 0.05 0.05 Tamb = 125 C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 Max 1.5 3.0 4.0 0.05 0.05 0.05 V V V V V V V V V V V V
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
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NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 6. Static characteristics ...continued VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter IOH Conditions VDD 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = -40 C Min HIGH-level VO = 2.5 V output current V = 4.6 V O VO = 9.5 V VO = 13.5 V IOL LOW-level VO = 0.4 V output current V = 0.5 V O VO = 1.5 V II IDD input leakage current supply current IO = 0 A; VI = VSS or VDD -1.7 -0.64 -1.6 -4.2 0.64 1.6 4.2 Max 0.1 5 10 20 Tamb = 25 C Min -1.4 -0.5 -1.3 -3.4 0.5 1.3 3.2 Max 0.1 5 10 20 7.5 Tamb = 85 C Min -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max 1.0 150 300 600 Tamb = 125 C Unit Min -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max 1.0 150 300 600 mA mA mA mA mA mA mA A A A A pF
11. Dynamic characteristics
Table 7. Dynamic characteristics Tamb = 25 C; VSS = 0 V; for test circuit see Figure 10 Symbol Parameter tPHL HIGH to LOW propagation delay Conditions VDD Extrapolation formula[1] 113 ns + (0.55 ns/pF) CL 44 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 118 ns + (0.55 ns/pF) CL 44 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 88 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 27 ns + (0.16 ns/pF) CL Min Typ 140 55 40 145 55 40 115 50 35 Max Unit 280 110 80 290 110 80 230 100 70 ns ns ns ns ns ns ns ns ns CP0, CP1 Q0 to Q9; 5 V see Figure 7 10 V 15 V CP0, CP1 Q5-9; see Figure 7 5V 10 V 15 V MR Q1 to Q9; see Figure 8 5V 10 V 15 V
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
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NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 7. Dynamic characteristics ...continued Tamb = 25 C; VSS = 0 V; for test circuit see Figure 10 Symbol Parameter tPLH LOW to HIGH propagation delay Conditions VDD Extrapolation formula[1] 98 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 98 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 83 ns + (0.55 ns/pF) CL 34 ns + (0.23 ns/pF) CL 27 ns + (0.16 ns/pF) CL 103 ns + (0.55 ns/pF) CL 44 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL
[2]
Min 90 40 20 80 40 30 80 40 30 80 40 30 50 30 20 60 30 20 6 12 15
Typ 125 50 40 125 50 40 110 45 35 130 55 40 60 30 20 45 20 10 40 20 10 40 20 15 40 20 15 25 15 10 30 15 10 12 30 30
Max Unit 250 100 80 250 100 80 220 90 70 260 105 75 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
CP0, CP1 Q0 to Q9; 5 V see Figure 7 10 V 15 V CP0, CP1 Q5-9; see Figure 7 5V 10 V 15 V MR Q5-9; see Figure 8 5V 10 V 15 V MR Q0; see Figure 8 5V 10 V 15 V 5V 10 V 15 V
tt
transition time
see Figure 7
10 ns + (1.00 ns/pF) CL 9 ns + (0.42 ns/pF) CL 6 ns + (0.28 ns/pF) CL
th
hold time
CP0 CP1; see Figure 9
5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V
CP1 CP0; see Figure 9
tW
pulse width
CP0 input LOW; minimum width; see Figure 8 CP1 input HIGH; minimum width; see Figure 8 MR input HIGH; minimum width; see Figure 8
trec
recovery time
MR input; see Figure 8
fmax
maximum frequency
see Figure 8
[1] [2]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). tt is the same as tTHL and tTLH.
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
8 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (W) PD = 500 x fi + (fo x CL) x VDD PD = 6000 x fi + (fo x CL) x
2
where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; (CL x fo) = sum of the outputs.
PD = 2200 x fi + (fo x CL) x VDD2 VDD2
12. Waveforms
VI CP0 input VSS VI CP1 input VSS tPHL VOH Q1 - Q9 output VOL tPLH VOH Q0, Q5 - Q9 output VOL VM tTLH tTHL 001aaj305 tPHL VM tPLH VM VM
Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition. CP1 triggers on a HIGH-to-LOW transition; The shaded areas indicate where the output state is set by the input count. Measurement points given in Table 9.
Fig 7.
Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition times
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
9 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
1/f max tW VI CP0 input VSS 1/f max VI CP1 input VSS VI MR input VSS tW VOH Q1 - Q9 output VOL tPHL VOH Q0, Q5 - Q9 output VOL tPLH VM
001aaj306
VM
VM tW trec VM
VM
Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition. tW and trec are measured when CP0 = HIGH and CP1 triggers on a HIGH-to-LOW transition; The shaded areas indicate where the output state is set by the input count. Measurement points given in Table 9.
Fig 8.
Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays
VI CP0 input VSS VI CP1 input VSS
001aae578
VM th th
VM
VM
VM
Hold times are shown as positive values, but may be specified as negative values; Measurement points given in Table 9.
Fig 9. Table 9. VDD
Waveforms showing hold times for CP0 to CP1 and CP1 to CP0 Measurement points Input VM 0.5VDD Output VM 0.5VDD
Supply voltage 5 V to 15 V
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
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NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
VDD VI G
RT
VO DUT
CL
001aag182
Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test; CL = load capacitance including jig and probe capacitance; RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 10. Test circuit Table 10. VDD 5 V to 15 V Test data Input VI VSS or VDD tr, tf 20 ns Load CL 50 pF
Supply voltage
13. Application information
Some examples of applications for the HEF4017B are:
* * * *
Decade counter with decimal decoding 1 out of n decoding counter (when cascaded) Sequential controller Timer
Figure 11 shows a technique for extending the number of decoded output states for the HEF4017B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
CP0
MR
CP0
MR
CP0
MR
HEF4017B
CP1 Q0 Q1- - - - Q8 Q9
HEF4017B
CP1 Q0 Q1- - - - Q8 Q9
HEF4017B
CP1 Q1 - - - - - - Q8 Q9
9 decoded outputs
8 decoded outputs
8 decoded outputs
clock
first stage
intermediate stages
last stage
001aae577
Enabling the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, causes an extra count.
Fig 11. Counter expansion
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
11 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
14. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 95-01-14 03-02-13
Fig 12. Package outline SOT38-4 (DIP16)
HEF4017B_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 9 December 2008
12 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 pin 1 index Lp 1 e bp 8 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 13. Package outline SOT109-1 (SO16)
HEF4017B_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 9 December 2008
13 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
15. Abbreviations
Table 11. Acronym DUT ESD HBM MM Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model
16. Revision history
Table 12. Revision history Release date 20081209 Data sheet status Product data sheet Change notice Supersedes HEF4017B_CNV_3 Document ID HEF4017B_4 Modifications:
* * * * * * * * * * * * * * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Rename the pins throughout to be consistent with rest of HEF family. Increased the maximum ambient temperature to 125 C throughout. Section 2 "Features" added. Package version SOT38-1 changed to SOT38-4 in Section 4, and Figure 12. Package SOT74 removed from Section 4. Table 1 "Ordering information" and Table 2 "Pin description" restructured. Figure 3 "Logic symbol" and Figure 4 "IEE logic symbol" added. Section 8 "Limiting values" and Section 10 "Static characteristics" added, taken from the HE4000B Family Specifications data sheet. Section 9 "Recommended operating conditions" added. Table 6 "Static characteristics" restructured. Values for IDD, IOL and IOH updated in Table 6 "Static characteristics". thold and tRMR renamed to th hold time and trec recovery time in Table 7 "Dynamic characteristics". and Section 12 "Waveforms". tWCPL, tWCPH and tWMRH renamed to tW minimum pulse width in Table 7 "Dynamic characteristics". and Section 12 "Waveforms". Figure 7 "Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition times" and Figure 10 "Test circuit" added. Maximum frequency and propagation added to Figure 8 "Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays". Section 14 "Package outline" added. Product specification Product specification HEF4017B_CNV_2 -
HEF4017B_CNV_3 HEF4017B_CNV_2
19950101 19950101
HEF4017B_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 9 December 2008
14 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4017B_4
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Product data sheet
Rev. 04 -- 9 December 2008
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NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
19. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 December 2008 Document identifier: HEF4017B_4

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